As is well known to those skilled in the art, a flash memory contains a memory cell array which is divided into multiple blocks (or referred to as "a sector") each of which comprises plural memory cells. In such a flash memory, an erasing operation is performed on a block-by-block basis.
The flash memory may contain up to, for example, 20 invalid blocks. The invalid blocks are defined as blocks that contain one or more invalid bits (or memory cells). The flash memories with one or more invalid blocks have the same quality level and AC and DC characteristics as a flash memory with all valid blocks. The invalid blocks do not affect the performance of valid blocks, because the invalid blocks are isolated from the bit line and the common source line (CSL) by a select transistor.
All blocks of the flash memory are erased (e.g. written to hexadecimal value ffh) prior to shipping. However, a flash memory with one or more invalid blocks will be programmed with complementary data, e.g. 00h (hereinafter referred to as "block status information") within the first page, the second page, or all pages of the one or more invalid blocks. These pages may or may not contain the invalid memory cells. The block status information identifies a block containing invalid memory cells so that the block may be avoided when the flash memory is programmed.
Referring to FIG. 1, there is a block diagram showing the structure of a PROM writer system 10 and the flow of signals between the system and plural flash memories 60. An example of the PROM writer system is described in U.S. Pat. No. 4,783,737, entitled PROM WRITER ADAPTED TO ACCEPT NEW WRITING ALGORITHM, the disclosure of which is hereby incorporated by reference. The '737 patent discloses a PROM writer system capable of writing data in a PROM via a writing algorithm stored in a memory that is different from the system program memory (so that the algorithm may be changed without change to the system program itself).
The system 10 (hereinafter referred to as "a PROM writer") is composed of a control unit 20, e.g. a central processing unit (CPU); a ROM unit 30 for storing a system program and a programming algorithm; a RAM unit 40 for storing data to be programmed in the flash memories 60a to 60d; and an interface unit 50. The control unit 20 reads the system program and the programming algorithm stored in the ROM unit 30 and writes the data stored in the RAM unit 40 to the flash memories 60a to 60d via the interface unit 50. The data bus for transmitting the data D0 to Di is shared by the flash memories 60a to 60d. Similarly, the address bus for transmitting the address signals A0 to Ai is shared by the flash memories 60a to 60d.
As shown in FIG. 1, a read enable signal RE and a write enable signal WE from the PROM writer 10 writer are driven in common to the four flash memories 60a to 60d, but the flash memories 60a, 60b, 60c and 60d are selected independently from each other when corresponding chip select signals CS0, CS1, CS2 and CS3 are activated, respectively.
FIG. 2 is a prior art flow chart showing the process of writing the same data in each of the plural flash memories 60a to 60d, under the control of the PROM writer 10 illustrated in FIG. 1. FIG. 3 shows a memory map of each flash memory illustrated in FIG. 1. In FIG. 3, the data stored in the RAM unit 40 may be written in remaining blocks BLK3 to BLKn (n: an integer) except for first and second blocks BLK1 and BLK2 of each flash memory 60a to 60d.
The programming process according to the prior art will be expressed below with reference to the accompanying drawings, with particular reference to FIG. 2.
At step S 11, a first flash memory 60a is selected by setting a variable DEVICE to `1`. That is, a first chip select signal CS0 from the PROM writer 10 becomes low (active). At step S12, one block BLK3 of multiple blocks BLK3 to BLKn of the selected flash memory 60a is selected by setting a variable BLOCK to `3`. Successively, in order to check whether the selected block BLK3 of the selected flash memory 60a is valid, block status information is read out from the selected block BLK3 of the selected flash memory 60a (step S13).
When the selected block BLK3 is determined to be a valid block by means of the control unit 20 of the PROM writer 10, the read block status information corresponding to the selected block BLK3 of the selected flash memory 60a is stored in the PROM writer 10, for example, in the RAM unit 40 of the PROM writer 10 (step S14) And then, the data stored in the RAM unit 40 is programmed in the selected block BLK3 of the selected flash memory 60a through the interface unit 50. When the selected block BLK3 is determined to be an invalid block by means of the control unit 20, the process proceeds to step S16 without programming for the selected block BLK3 after storing the block status information of the selected block BLK3. In other words, the programming operation for the selected block BLK3 is skipped.
At step S16, the control unit 20 of the PROM writer 10 checks whether the selected block BLK3 is a last block to be programmed. If the selected block BLK3 is not a last block, the process proceeds to step S18, in which the variable BLOCK is increased by one so as to assign a next block. The process from step S13 to step SI 8 is repeated until a selected block is determined as a last block to be programmed.
When a selected block is discriminated as a last block, file allocation table (FAT) data in accordance with the block status information, which has been stored temporarily in the RAM unit 40, is programmed in the first or second block BLK1 or BLK2 of the selected flash memory 60a (step S19).
The term "file allocation table" may also be referred to as a "flash file system". A suitable flash file system is more fully described in U.S. Pat. No. 5,404,485, entitled FLASH FILE SYSTEM, the disclosure of which is hereby incorporated by reference.
The process from step S12 to step S18 is repeated until the remaining flash memories 60b to 60d are programmed with the same data as stored in the RAM unit 40, via the process of steps S20 and S21.
When the programming process is finished, the contents of each of the flash memories 60a to 60d is illustrated by the memory map of FIG. 4. As seen in FIG. 4, the data to be programmed in an invalid block is stored instead in a next valid block, as indicated by curved arrows.
As set forth above, the flash memories 60a to 60d which may have one or more invalid blocks are programmed by means of a serial programming process, thereby increasing the time required for the programming process, according to the prior art.